-- Vhdl test bench created from schematic biili.sch - Wed Nov 22 13:06:08 2006
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY biili_biili_sch_tb IS
END biili_biili_sch_tb;
ARCHITECTURE behavioral OF biili_biili_sch_tb IS 

   COMPONENT biili
   PORT( moottori_o_p98	:	OUT	STD_LOGIC; 
          moottori_v_p49	:	OUT	STD_LOGIC; 
          suunta_v_p83	:	OUT	STD_LOGIC; 
          suunta_o_p84	:	OUT	STD_LOGIC; 
          clock_p80	:	IN	STD_LOGIC; 
          anturi0_p161	:	IN	STD_LOGIC; 
          anturi1_p162	:	IN	STD_LOGIC; 
          anturi2_p163	:	IN	STD_LOGIC; 
          reset_p55	:	IN	STD_LOGIC);
   END COMPONENT;

   SIGNAL moottori_o_p98	:	STD_LOGIC;
   SIGNAL moottori_v_p49	:	STD_LOGIC;
   SIGNAL suunta_v_p83	:	STD_LOGIC;
   SIGNAL suunta_o_p84	:	STD_LOGIC;
   SIGNAL clock_p80	:	STD_LOGIC;
   SIGNAL anturi0_p161	:	STD_LOGIC;
   SIGNAL anturi1_p162	:	STD_LOGIC;
   SIGNAL anturi2_p163	:	STD_LOGIC;
   SIGNAL reset_p55	:	STD_LOGIC;

BEGIN

   UUT: biili PORT MAP(
		moottori_o_p98 => moottori_o_p98, 
		moottori_v_p49 => moottori_v_p49, 
		suunta_v_p83 => suunta_v_p83, 
		suunta_o_p84 => suunta_o_p84, 
		clock_p80 => clock_p80, 
		anturi0_p161 => anturi0_p161, 
		anturi1_p162 => anturi1_p162, 
		anturi2_p163 => anturi2_p163, 
		reset_p55 => reset_p55
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;
