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-- Company: 
-- Engineer:
--
-- Create Date:   10:39:21 12/14/2006
-- Design Name:   kierroslulkulaskuri
-- Module Name:   kierros_test.vhd
-- Project Name:  auto
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: kierroslulkulaskuri
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY kierros_test_vhd IS
END kierros_test_vhd;

ARCHITECTURE behavior OF kierros_test_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT kierroslulkulaskuri
	PORT(
		anturit : IN std_logic_vector(2 downto 0);
		clock : IN std_logic;          
		arvo : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clock :  std_logic := '0';
	SIGNAL anturit :  std_logic_vector(2 downto 0) := (others=>'0');

	--Outputs
	SIGNAL arvo :  std_logic_vector(3 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: kierroslulkulaskuri PORT MAP(
		anturit => anturit,
		clock => clock,
		arvo => arvo
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
