library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity aani is
    Port ( clock : in std_logic;
	 		  aanta : in std_logic;
			  aani_out : out std_logic
			  );
end aani;

architecture Behavioral of aani is
	
signal count :integer :=0;
signal aani_sig : std_logic :='0';
begin

process (clock) 

begin

  if clock='0' and clock'event and aanta = '1' then

	count <= count +1;
	if count = (32000000/2500)/2 then
		count <= 0;
		aani_sig <= aani_sig xor '1';
		aani_out <= aani_sig;
	end if;

	end if;
 
end process;

end Behavioral;